Post
by thewisepranker » Mon Jul 05, 2021 10:13 pm
In that circuit you can't just drop in a 7400 without adding current limiting resistors on output pins 3 and 6, not that I suggest doing so.
The two NAND gates form an OR gate with R10. This works for open collector outputs but if for example pin 6 is high and pin 3 is low, pin 6 will be shorted to ground. It probably won't blow up but it will be dissipating quite a bit of power in the limiting resistor of the gate with output pin 6.
It'd be better to redesign it and make use of the fourth gate, without having to sum two outputs together as shown above. If you can't do it with four gates, perhaps try a different type of gate instead - you might be able to map it to four NOR gates.
What is U1?
Something funny is going on around D1, there's no path to ground, unless it's through pin 2 of J2?