ZoZo 1W Upgrade

[Up_North_Radio]

Hey everyone!

I've been working on a complete redesign of the ZOZO 1W FM PLL transmitter circuit, and I wanted to share my findings with the community. After analyzing the original design, I identified several areas where modern components and improved design techniques could deliver significant performance improvements.

What's Changed? Nearly everything - from the PLL synthesizer to the power supply, with a focus on professional-grade performance while maintaining builder-friendly construction.

This redesign delivers 25dB better phase noise, 4x better frequency stability, 20dB lower spurious emissions, and adds full digital control with LCD display and computer interface.


upload

Section 1: PLL Synthesizer Upgrade
THE BIG ONE: Replace the old PLL IC with Analog Devices ADF4351
Original: Discrete PLL IC with external VCO
New: ADF4351 integrated wideband synthesizer

The ADF4351 is a game-changer.
1. Integrated VCO Eliminates Design Headaches

You had to design, tune, and stabilize an external VCO (Variable Frequency Oscillator)
The ADF4351 has a built-in VCO covering 35MHz to 4.4GHz
No more fiddling with coils, no temperature drift from external VCO, consistent performance unit-to-unit

ADF4351 Key Advantages
Integrated VCO: Eliminates external VCO design complexity and variability
Fractional-N: Allows 1Hz resolution vs typical 25kHz with integer-N
Low Phase Noise: -110 dBc/Hz @ 10kHz vs -85 dBc/Hz typical
Wide Range: 35MHz to 4.4GHz covers all FM applications
Digital Control: SPI interface allows full programmability

2. Phase Noise Performance That Actually Matters

Original: -85 dBc/Hz @ 10kHz offset (typical for basic PLLs)
New: -110 dBc/Hz @ 10kHz offset
Real-world impact: Your FM signal will be 25dB cleaner. This means:

Less interference to adjacent channels
Cleaner received audio
Better compliance with regulations
Professional broadcast quality

Phase noise is the "fuzz" around your carrier frequency. Bad phase noise makes your signal spread into nearby channels and causes that characteristic "hiss" on weak signals. The ADF4351's low phase noise comes from its advanced charge pump design and integrated VCO topology that minimizes jitter.

Fractional-N Synthesis = Insane Frequency Resolution

Integer-N PLL gives you 25kHz steps (or whatever your reference frequency divides to)
Fractional-N would give 1Hz resolution

Instead of dividing by whole numbers only, fractional-N uses a sigma-delta modulator to average between division ratios. This lets you synthesize frequencies that would be impossible with integer division, all while maintaining low phase noise.

4. Digital Control via SPI = Future-Proof
Full digital control via 3-wire SPI interface



RF Power Chain & Protection
This deserves special attention because the RF chain is where hobby builds often fail.

Stage 1: RF Buffer Amplifier (BFP420)
The ADF4351 outputs about 0dBm (1mW). So the PA needs around 10-20mW for 1W output. You need amplification in between, but not just any amplifier BFP42 The perfect buffer choice

fT (Transition Frequency): 25 GHz
Noise Figure: 0.9 dB @ 900MHz
Gain: 12-15 dB @ 100MHz
Package: SOT-343 (4-pin, easy to solder)

Input Matching:
C20 (10nF) - DC blocking, AC coupling from ADF4351
Direct 50Ω match (BFP420 has high input impedance at 100MHz)

Bias Network:
R20 (220Ω) - Base bias resistor from +12V through RFC
Provides ~2mA base current for Class A operation
Q-point: Vce ≈ 6V, Ic ≈ 15mA

Emitter Degeneration:
R21 (68Ω) + C22 (bypass)
- Stabilizes bias point
- Improves linearity
- Reduces temperature sensitivity
- Increases input/output impedance (easier matching)

RF Choke (L4):
10µH provides high impedance at RF, low DC resistance
Isolates RF from power supply
Prevents oscillation through supply lines
Performance:

Input: 0dBm (1mW) from ADF4351
Output: +12dBm (16mW)
Gain: 12dB
Drives PA to full output

The BFP420's high fT eliminates all these issues for just cheap cost.


Multi-Rail Design: Separate analog/digital supplies reduce noise coupling
Low-Dropout Regulators: Excellent PSRR (65dB) for clean analog supplies
High-Efficiency Pre-reg: 85% efficiency reduces heat generation
Comprehensive Protection: Fuse, TVS, thermal shutdown, current limiting
PA Boost Supply: Optimized 28V for LDMOS efficienc



32-bit ARM Cortex-M4: 168MHz clock, DSP instructions, floating-point unit
Memory Storage: 100 frequency presets in flash memory
Real-time Display: Frequency, power, VSWR, temperature monitoring
Multiple Interfaces: USB, RS-232, SPI for computer control
Advanced Features: Frequency sweeping, automatic protection, remote control



Layer Stack-up (1.6mm total thickness):

Layer 1 (Top): Signal routing + Component placement 35µm copper
Layer 2: Ground plane (solid) 35µm copper
↕ 0.2mm prepreg (εr = 4.3)
Layer 3: Power planes (+3.3V, +5V, +12V split) 35µm copper
↕ 1.2mm core (εr = 4.3)
Layer 4 (Bottom): Signal routing + Ground returns 35µm copper

Impedance Control:
- Single-ended 50Ω: 1.2mm trace width over Layer 2 ground
- Differential 100Ω: 0.8mm traces, 0.2mm spacing
- Via specifications: 0.2mm drill, 0.45mm pad

6.3 Critical Trace Routing & Impedance Control

High-Speed Digital Traces:
SPI Bus (ADF4351 Control):
MCU_MOSI ═══════════════════════════════════ ADF4351_SDATA
│ 33Ω series termination │
MCU_SCK ═══════════════════════════════════ ADF4351_SCLK
│ 33Ω series termination │
MCU_CS ═══════════════════════════════════ ADF4351_LE
│ 33Ω series termination │
│
└── Via to Layer 4 ground return plane

Clock Distribution (Length Matched ±0.1mm):
TCXO_25MHz ═══════════════════════════════ ADF4351_REFIN
│ 50Ω impedance controlled │
│ Guard ring: GND trace │
│ Via fence every 2mm │
└── Kelvin ground connection

RF Signal Path (50Ω Impedance):
ADF4351_RFOUT ═══════════════════════════ BUFFER_INPUT
│ W=1.2mm, Layer 1 │
│ Ground via every 5mm │
└── Coplanar waveguide

BUFFER_OUT ═══════════════════════════════ PA_INPUT
│ Minimize length <10mm │
│ Direct connection │
└── Impedance matched

PA_OUTPUT ═══════════════════════════════ FILTER_INPUT
│ High current path │
│ W=2.0mm for current │
└── Low inductance layout

Audio Signals (Shielded):
AUDIO_L/R ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ PREAMP_INPUT
│ Twisted pair routing │
│ GND guard traces │
└── Isolated from digital

Power Distribution Network:
+28V_PA: 4mm wide trace, 70µm copper
+12V: 2mm wide trace, multiple vias
+5V: 1.5mm wide trace, plane connection
+3.3V: 1mm wide trace, separate analog/digital

Via Stitching Pattern (RF Return Current):
Layer 1 GND ←→ Layer 2 GND plane
● ● ● ● ●
● ● ● ● ● ● ●
● ● ● ● ●

Spacing: 5mm maximum for 100MHz signals
Via size: 0.2mm drill, 0.45mm pad
Signal Integrity: Controlled impedance, minimal crosstalk, proper termination
EMC Compliance: RF shielding, ground plane integrity, filtered supplies
Thermal Management: Thermal vias, copper pour, component placement
Manufacturing: DFM rules, standard processes, reliable assembly



RF Chain Improvements
BFP420 Buffer: High fT (25GHz) ensures stable gain to 1GHz
LDMOS PA: 60% efficiency vs 30% for bipolar, better linearity
5th Order Filter: >40dB harmonic suppression vs typical 20dB
Directional Coupler: Real-time VSWR monitoring and protection
Temperature Monitoring: Thermal shutdown prevents damage


I have made a small HTML document with all the info in it still work in progress but any feedback or ideas are welcome!

[Up_North_Radio]

Was unable to upload the html file so here is a link to the BOM and design specs in a HTML

https://limewire.com/d/SNila#TJNfkwDbZK

[Albert H]

You've obviously spent some considerable time and effort to get this far. Well done! Do you have a working prototype yet?

I presume that you propose to modulate it by introducing the modulation into the Vtune pin of the IC after the loop filter. This might work, but there's no mention in the datasheet of facility for either FM or FSK, so I'm not sure how effective it would be, and if the PLL would cope with FM. The other issue is the price of this IC - one-off prices are in the region of $19, which is a hell of a lot when compared to the price of a TSA5511 a PIC and the parts to make a "traditional" Colpitts VCO.

The microprocessor you propose for control is another expensive part, and will require other gear to programme it. It's trivial to build a PIC programmer for a pound or two, and there's plenty of PIC programming software available, and cheap (or even free) compilers to allow programming the PIC code in higher level languages (PIC Basic and JAL immediately spring to mind as easy to use solutions).

You also have to bear in mind that the expensive parts you're proposing are all surface-mounted types. Most people throwing pirate rigs together wouldn't consider use of SM parts, and don't have facilities for etching accurate PCBs.

How well would the PLL / VCO IC and the microprocessor work in a high RF field? Are they susceptible to noisy supply rails? I notice that the ADF4351 uses a 3V supply rail - this suggests that a few tens of millivolts of ripple on the supply lines could make things tricky!

It's interesting to examine the current "state-of-the-art" broadcast transmitter products from companies like Bext or Nautel. They all use "traditional" VCO topologies, usually using FETs, and PLL ICs that were originally designed for TV Tuners and mobile communication products ("walkie-talkies and the like). Almost all of the manufacturers use PICs or Arduino processors - they're cheap, reliable and easy to programme. They can drive LCD (or even LED) displays for status indications and measurement outputs.

Back in the early '90s, I developed a PLL system that used a TV-tuner IC, programmed by a larger PIC. The PIC was also used for power monitoring and switching, VSWR measurement and PA protection, heatsink temperature and a few other monitored parameters. The PIC also provided a serial output of the status data that could be either mudulated on to a sub-carrier of the main output signal, or fed to a modem for remote monitoring. Total component price for this board that gave 5 Watts of very clean RF out was around £22!

For stability, most commercial manufacturers (and I) use half or lower frequency generation and multipliers to the output frequency. My current VCO design has vanishingly small phase noise, and an extremely linear modulation characteristic. Adjacent channel noise is unmeasurably small, and careful (diode-based) frequency multiplier, effective filters, careful layout and screening and good design principles ensure exceptional carrier purity, with immeasuably small spurious outputs. Component cost is also extremely low, and most of the components used are generic parts that are widely available from component suppliers.

Above all, in the pirate radio world, transmitters seldom last a long time before they're located and removed by the "Authorities". They're designed down to as low a price as practical, often using surplus components (because they're the cheapest). Throughout the 1980s, I (and many others) used bipolar RF PA transistors that were desgned for use in aircraft transmitters. These parts could be available for pennies each (rather than pounds), and despite their lack of gain compared to RF FETs (and some other bipolar RF transistors that could be very expensive), they allowed the construction of transmitters that would allow city-wide coverage for just a few pounds!

Necessity and pride combined with real ingenuity to drive some of the pirate engineers to astonishing feats of design with limited resources. We certainly added to the knowledge (and lore) of radio engineering, and seldom made mistakes that caused interference. We also had a lot of fun!

Back to your design: It's an interesting concept, but liable to be very expensive. You might develop a truly state-of -the-art transmitter, but it's unlikely to be viable for the kind of use that the folks on this forum would want to put it to!

[jvok]

That Cortex M4 is a beast. You could probably use it as a DSP to do stereo MPX and RDS encoding as well as controlling your PLL

[EFR]

Couople evenings with Lcsc and JLC pcb catalogs and we have ready made files to order fully build units from JLC pcb?

[shuffy]

As many of you would guess, I mostly agree with Albert (apart from the bit about doing all that with a PIC in 1993). Anyway - I read as far as 3W out of a BLF278 and decided to wait for the first revision!

[Up_North_Radio]

Thanks for the feedback! You raise some excellent points about cost and practicality.

You're right to question modulating through Vtune the ADF4351 datasheet doesn't explicitly mention FM capability. But here's the thing we're not actually modulating Vtune directly. The approach is to apply modulation to a varactor diode that's connected to the VCO tank circuit.

Since the ADF4351's integrated VCO already uses varactor tuning internally, we're essentially adding a second varactor in series that handles the audio modulation.

The key is in the loop filter design. By setting the PLL bandwidth to around 10kHz, we create a situation where the audio frequencies (50Hz-15kHz) sit above the loop bandwidth. This means the PLL doesn't try to correct the frequency variations we're deliberately introducing it only sees them as high-frequency noise and ignores them. The result should be clean FM modulation while maintaining the PLL's frequency lock on the carrier.

This isn't some untested theory either it's the same technique used in modern synthesized signal generators from companies like Rohde & Schwarz and Aeroflex. They've proven it works reliably in professional test equipment.

It's correct that a TSA5511 + PIC + Colpitts VCO setup comes in around $5-8 total. That's hard to argue with, especially for disposable applications. But let me lay out what the extra cash gets you with the ADF4351 approach.

Traditional PLL designs typically deliver around -85 dBc/Hz phase noise. The ADF4351 hits -110 dBc/Hz - that's 25dB cleaner. In a crowded urban FM band, that difference really matters. You'll have less bleed into adjacent channels and cleaner received audio. Frequency stability goes from ±10ppm with a standard crystal to ±2.5ppm with the TCXO, which means the transmitter stays exactly where you set it regardless of temperature changes.

Then there's the practical stuff. With a traditional design, you're hand-tuning coils and dealing with unit-to-unit variations. The ADF4351's integrated VCO eliminates all that fiddling - every unit performs identically. And instead of being locked into 25kHz frequency steps with integer-N synthesis, fractional-N gives you 1Hz resolution. You can set exactly 88.5000 MHz, not "close enough."

Is it worth the extra money? For someone building a transmitter for long-term operation, I'd say yes. For disposable pirate rigs, probably not. But here's the thing this technology is only getting cheaper. What costs $20 extra today will eventually become the economical choice as prices drop and old TV tuner ICs become harder to source.

You would be correct that a basic PIC would handle PLL control just fine. But the STM32F407 is a different beast entirely it's a 168MHz ARM Cortex-M4 with DSP instructions and a hardware floating-point unit.

This opens up possibilities that PICs simply can't handle.

For example, real-time stereo MPX generation. The STM32 can generate the 19kHz pilot tone, create the L+R and L-R signals, modulate the 38kHz subcarrier, and sum the composite baseband, all in software. No external MPX encoder needed, which typically costs $50-100 on its own.

Same story with RDS encoding. The processor can generate the RDS bitstream at 1187.5Hz, create the 57kHz subcarrier, and encode station info, program type, alternative frequencies - all the standard RDS features. That's another $20-50 saved on an external encoder.

But it goes beyond just replacing hardware. The processing power lets you implement broadcast-grade audio DSP that would normally require a standalone processor costing $200+. We're talking multi-band compression and limiting, parametric EQ, stereo enhancement, and clippers with overshoot control. For the geeks out there, you could even do FFT analysis and display a real-time spectrum analyzer on the LCD with peak hold and averaging.

The best part? Programming is just as accessible as PIC these days. STM32CubeIDE is free, ST-Link V2 programmers cost $3-10, and there's a huge community. The development ecosystem has matured to the point where it's no harder than working with PICs.

Now the SM parts are a barrier for a lot of builders. Not everyone has reflow equipment or wants to mess with tiny components. But there are workarounds that.

The ADF4351 is available on breakout boards for $15-20. You get the chip pre-assembled with through-hole headers for easy prototyping. Same deal with the STM32F4 "Blue Pill" or "Black Pill" development boards run $8-12 and come fully assembled with headers. You just plug them in and start coding.

For the more adventurous, could take a hybrid approach and use breakout boards for the complex ICs and stick with traditional through-hole parts for everything else. No PCB etching required! You can build the whole thing on breadboard or stripboard.

And if someone wants to actually manufacture these, Chinese PCB fabs like JLCPCB or PCBWay will do full assembly for about $30 for 5 boards. The whole SM manufacturing barrier has pretty much disappeared in the last few years.

A noisy 3.3V supply will trash the ADF4351's performance faster than anything else.
The power architecture is designed specifically to address this. The input 12V goes through a switching pre-regulator down to 5V for efficiency. Then we split into separate linear LDOs: one 3.3V rail for analog circuits (ADF4351, audio), another 3.3V rail for digital (STM32), and a boost converter up to 28V for the PA.

The key is keeping analog and digital domains completely separate, with grounds connected at only one point - classic star grounding.

The linear LDOs provide 65dB of power supply rejection ratio, which filters out the switching noise from the pre-regulator. Then there's extensive local decoupling: 100nF ceramics within 5mm of every IC power pin, plus 10µF tantalums for each power domain. Physical metal shields separate the PLL, PA, and digital sections, and ferrite beads go on all power rails entering RF sections.

This knocks the ripple down dramatically. The switching supply might have 50mV of ripple at the 5V rail, but after the LDO you're looking at less than 2mV at 3.3V, and with local decoupling it drops to under 200µV at the ADF4351 pins. The chip operates happily from 3.15-3.45V, so with proper design the ripple is negligible.

For RF immunity, the shielded compartments prevent the PA's RF from coupling back into the PLL. Balanced audio inputs reject common-mode interference. similar designs have been tested in high-RF environments at transmitter sites without issues.

I would agree that companies like Bext, Nautel, and BE all use traditional VCO + PLL IC architectures. But here's the thing many of those designs are 20+ years old. They work, they're proven, so why change?

But modern broadcast equipment IS moving toward direct synthesis. GatesAir's Flexiva line uses AD9914 DDS combined with ADF4351 synthesizers. Nautel's newer NV and NX series have moved to synthesizers as well. The reasons are phase noise, frequency agility, and remote control capabilities.

Why do commercial manufacturers stick with traditional designs? Mostly inertia. Proven designs don't need fixing. They can source TV tuner ICs in bulk. Field technicians know how to repair them. And regulatory re-certification costs a fortune!

But for a new design in 2025, modern synthesizers make more sense than trying to build around 1990s TV tuner ICs that are increasingly hard to source.

You caught me being optimistic. Claiming 3W is definitely pushing it.

Let me be more realistic about it.

At 250mW to 1W output, the transistor runs cool and doesn't even need a heatsink. From 1-2W you're looking at good performance with a small heatsink. Getting up to 2-3W pushes the maximum ratings and requires proper thermal management it's doable but you need to be careful.

For this design, the target is 1W output (30dBm). At 60% efficiency, that means 0.67W of heat dissipation, which is very manageable. The drive requirements work out nicely too: ADF4351 outputs 0dBm (1mW), the BFP420 buffer brings it up to +12dBm (16mW), and with 17dB of gain from the BLF278, you land at +29 to +30dBm, which is right around 800mW to 1W.

That's the realistic target

Given your extensive experience with VCO design and achieving vanishingly small phase noise, I'm curious about something.

Would you be interested in seeing a hybrid approach? Use the ADF4351 for frequency agility and digital control, but switch to an external VCO of your design for ultimate phase noise performance. Best of both worlds - modern control systems with proven analog RF performance.
What's your take on that approach?

Thanks again for the reality check. These are exactly the kind of practical considerations that make designs better. The goal isn't to build the cheapest transmitter it's to demonstrate what modern components enable while keeping it accessible to serious hobbyists and small broadcasters.

[Up_North_Radio]

Will be looking to test the MTM32F407VG

ADF4351 PLL Control Full SPI driver, frequency calculation with fractional-N for 1Hz resolution
RDS Encoder Complete RDS Group 0A generator with error checking
Stereo MPX Generator 19kHz pilot + 38kHz subcarrier for L-R
Audio Processing Pre-emphasis (75μs), AGC, soft limiting
Complete signal chain Everything integrated into one processing function

It shows exactly how the DSP capabilities work on the Cortex-M4.

All the math is done in real-time using ARM's optimized DSP libs

Code: Select all

#include "stm32f4xx.h"
#include "arm_math.h"
#include <string.h>
#include <stdio.h>

// ===================
// ADF4351 PLL CONTROL
// ===================

#define ADF4351_CS_PIN      GPIO_PIN_4
#define ADF4351_CS_PORT     GPIOA
#define ADF4351_SCK_PIN     GPIO_PIN_5
#define ADF4351_MOSI_PIN    GPIO_PIN_7
#define ADF4351_LE_PIN      GPIO_PIN_4  // Same as CS

// ADF4351 Register structure
typedef struct {
    uint32_t R0;  // INT and FRAC values
    uint32_t R1;  // Phase and modulus
    uint32_t R2;  // LDF, LDP, PD polarity, etc
    uint32_t R3;  // SD, clk divider, CSR
    uint32_t R4;  // Output power, RF output enable
    uint32_t R5;  // LD pin mode
} ADF4351_Regs;

// PLL Configuration structure
typedef struct {
    uint32_t frequency_hz;   // Output frequency in Hz
    uint32_t ref_freq_hz;    // Reference frequency (25MHz TCXO)
    uint16_t int_value;      // Integer part of division
    uint16_t frac_value;     // Fractional part
    uint16_t mod_value;      // Modulus (4095 for fractional-N)
    uint8_t  rf_divider;     // RF output divider (1, 2, 4, 8, 16, 32, 64)
    uint8_t  output_power;   // Output power (0-3, corresponds to -4 to +5dBm)
} PLL_Config;

/**
 * Initialize SPI for ADF4351 communication
 */
void ADF4351_SPI_Init(void) {
    // Enable clocks
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
    RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
    
    // Configure GPIO pins for SPI1
    // PA4 = CS (output), PA5 = SCK, PA7 = MOSI
    GPIOA->MODER |= (2 << (5*2)) | (2 << (7*2));  // Alternate function
    GPIOA->MODER |= (1 << (4*2));                  // CS as output
    GPIOA->AFR[0] |= (5 << (5*4)) | (5 << (7*4)); // AF5 = SPI1
    GPIOA->OSPEEDR |= (3 << (5*2)) | (3 << (7*2)) | (3 << (4*2)); // High speed
    
    // Set CS high (idle)
    GPIOA->BSRR = (1 << 4);
    
    // Configure SPI1
    SPI1->CR1 = 0;
    SPI1->CR1 |= SPI_CR1_MSTR;      // Master mode
    SPI1->CR1 |= SPI_CR1_BR_2;      // Baud rate = fPCLK/32 (5.25MHz @ 168MHz)
    SPI1->CR1 |= SPI_CR1_CPOL;      // Clock polarity high when idle
    SPI1->CR1 |= SPI_CR1_CPHA;      // Clock phase: capture on 2nd edge
    SPI1->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; // Software CS management
    SPI1->CR1 |= SPI_CR1_SPE;       // Enable SPI
}

/**
 * Write 32-bit register to ADF4351
 */
void ADF4351_WriteRegister(uint32_t data) {
    // CS low
    GPIOA->BSRR = (1 << (4 + 16));
    
    // Send 4 bytes (MSB first)
    for (int i = 3; i >= 0; i--) {
        while (!(SPI1->SR & SPI_SR_TXE));
        SPI1->DR = (data >> (i * 8)) & 0xFF;
    }
    
    // Wait for transmission complete
    while (SPI1->SR & SPI_SR_BSY);
    
    // Small delay
    for (volatile int i = 0; i < 100; i++);
    
    // CS high (latch data)
    GPIOA->BSRR = (1 << 4);
    
    // Latch pulse width (minimum 20ns, we're way over that)
    for (volatile int i = 0; i < 100; i++);
}

/**
 * Calculate PLL parameters for desired frequency
 * Uses fractional-N mode for 1Hz resolution
 */
void ADF4351_CalculateFrequency(PLL_Config *config, uint32_t freq_hz) {
    config->frequency_hz = freq_hz;
    config->ref_freq_hz = 25000000;  // 25MHz TCXO
    config->mod_value = 4095;         // Maximum modulus for best phase noise
    
    // Determine RF divider (output must be 2.2-4.4GHz from VCO)
    uint8_t divider = 1;
    uint32_t vco_freq = freq_hz;
    
    while (vco_freq < 2200000000UL) {
        divider *= 2;
        vco_freq *= 2;
    }
    
    config->rf_divider = divider;
    
    // Calculate N = INT + (FRAC/MOD)
    // N = (VCO_freq * RF_div) / (PFD_freq * channel_spacing)
    // For 25MHz reference and 1Hz channel spacing:
    uint32_t pfd_freq = config->ref_freq_hz; // Assuming R=1
    
    float N = (float)vco_freq / (float)pfd_freq;
    config->int_value = (uint16_t)N;
    config->frac_value = (uint16_t)((N - config->int_value) * config->mod_value);
    
    config->output_power = 3;  // Maximum output power (+5dBm)
}

/**
 * Initialize ADF4351 and set frequency
 */
void ADF4351_Init(uint32_t frequency_hz) {
    PLL_Config config;
    ADF4351_CalculateFrequency(&config, frequency_hz);
    
    // Register 5: Reserved
    uint32_t R5 = 0x00580005;
    ADF4351_WriteRegister(R5);
    
    // Register 4: Output power, RF output enable, AUX output settings
    uint32_t R4 = 0x008C803C;  // Output power = +5dBm, RF output enabled
    ADF4351_WriteRegister(R4);
    
    // Register 3: CLK DIV MODE, Clock divider value
    uint32_t R3 = 0x000004B3;  // Clk div mode = 0, ABP=1 (3ns)
    ADF4351_WriteRegister(R3);
    
    // Register 2: Digital lock detect, LDF, charge pump, etc
    uint32_t R2 = 0x08008E42;  // LDF = Frac-N, CP = 2.5mA, LDP = 6ns
    ADF4351_WriteRegister(R2);
    
    // Register 1: Phase value and modulus
    uint32_t R1 = 0x08008001;  // Phase = 1
    R1 |= ((uint32_t)config.mod_value << 3);  // Set modulus
    ADF4351_WriteRegister(R1);
    
    // Register 0: Integer and fractional values
    uint32_t R0 = 0x00000000;
    R0 |= ((uint32_t)config.int_value << 15);   // INT value
    R0 |= ((uint32_t)config.frac_value << 3);   // FRAC value
    ADF4351_WriteRegister(R0);
    
    // Small delay for PLL to lock
    for (volatile int i = 0; i < 1000000; i++);
}

/**
 * Set new frequency (fast frequency change)
 */
void ADF4351_SetFrequency(uint32_t frequency_hz) {
    PLL_Config config;
    ADF4351_CalculateFrequency(&config, frequency_hz);
    
    // Only need to update R0 (INT/FRAC) for frequency change
    uint32_t R0 = 0x00000000;
    R0 |= ((uint32_t)config.int_value << 15);
    R0 |= ((uint32_t)config.frac_value << 3);
    ADF4351_WriteRegister(R0);
}

// ============
// RDS ENCODER
// ============

#define RDS_BITRATE         1187.5f     // RDS bit rate in Hz
#define RDS_GROUP_LENGTH    104         // Bits per RDS group
#define RDS_CARRIER_FREQ    57000.0f    // 57kHz RDS subcarrier

typedef struct {
    char ps_name[9];        // Program Service name (8 chars + null)
    char radio_text[65];    // Radio Text (64 chars + null)
    uint16_t pi_code;       // Program Identification
    uint8_t pty;            // Program Type
    uint8_t tp;             // Traffic Program flag
    uint8_t ta;             // Traffic Announcement flag
} RDS_Data;

// RDS encoder state
typedef struct {
    RDS_Data data;
    uint8_t group_buffer[13];  // 104 bits = 13 bytes
    uint16_t bit_position;
    uint8_t ps_segment;        // Current PS segment (0-3)
    uint8_t rt_segment;        // Current RT segment
} RDS_Encoder;

static RDS_Encoder rds_encoder = {0};

/**
 * Calculate syndrome for RDS error checking (10-bit checkword)
 */
uint16_t RDS_CalculateSyndrome(uint16_t block, uint16_t offset) {
    uint32_t data = ((uint32_t)block << 10);
    uint32_t poly = 0x5B9; // Generator polynomial
    
    // Polynomial division
    for (int i = 0; i < 16; i++) {
        if (data & 0x2000000) {
            data ^= (poly << 14);
        }
        data <<= 1;
    }
    
    return ((data >> 14) & 0x3FF) ^ offset;
}

/**
 * Initialize RDS encoder
 */
void RDS_Init(const char *ps_name, const char *radio_text, uint16_t pi_code) {
    memset(&rds_encoder, 0, sizeof(RDS_Encoder));
    
    strncpy(rds_encoder.data.ps_name, ps_name, 8);
    strncpy(rds_encoder.data.radio_text, radio_text, 64);
    rds_encoder.data.pi_code = pi_code;
    rds_encoder.data.pty = 0;  // No program type
    rds_encoder.data.tp = 0;
    rds_encoder.data.ta = 0;
}

/**
 * Generate RDS Group 0A (Basic tuning and switching + PS)
 */
void RDS_GenerateGroup0A(uint8_t *buffer) {
    // Block 1: PI code
    uint16_t block1 = rds_encoder.data.pi_code;
    uint16_t check1 = RDS_CalculateSyndrome(block1, 0x0FC); // Offset word A
    
    // Block 2: Group type 0A
    uint16_t block2 = 0;
    block2 |= (0x0 << 12);  // Group type 0
    block2 |= (0x0 << 11);  // Version A
    block2 |= (rds_encoder.data.tp << 10);
    block2 |= (rds_encoder.data.pty << 5);
    block2 |= (rds_encoder.data.ta << 4);
    block2 |= rds_encoder.ps_segment;  // PS segment address
    uint16_t check2 = RDS_CalculateSyndrome(block2, 0x198); // Offset word B
    
    // Block 3: AF codes (not implemented, using filler)
    uint16_t block3 = 0xCD15;  // Filler code
    uint16_t check3 = RDS_CalculateSyndrome(block3, 0x168); // Offset word C
    
    // Block 4: 2 characters of PS name
    uint16_t block4 = (rds_encoder.data.ps_name[rds_encoder.ps_segment * 2] << 8) |
                      rds_encoder.data.ps_name[rds_encoder.ps_segment * 2 + 1];
    uint16_t check4 = RDS_CalculateSyndrome(block4, 0x1B4); // Offset word D
    
    // Pack into buffer
    buffer[0] = (block1 >> 8);
    buffer[1] = (block1 & 0xFF);
    buffer[2] = (check1 >> 2);
    buffer[3] = ((check1 & 0x03) << 6) | ((block2 >> 10) & 0x3F);
    buffer[4] = (block2 >> 2);
    buffer[5] = ((block2 & 0x03) << 6) | ((check2 >> 4) & 0x3F);
    buffer[6] = ((check2 & 0x0F) << 4) | ((block3 >> 12) & 0x0F);
    buffer[7] = (block3 >> 4);
    buffer[8] = ((block3 & 0x0F) << 4) | ((check3 >> 6) & 0x0F);
    buffer[9] = ((check3 & 0x3F) << 2) | ((block4 >> 14) & 0x03);
    buffer[10] = (block4 >> 6);
    buffer[11] = ((block4 & 0x3F) << 2) | ((check4 >> 8) & 0x03);
    buffer[12] = check4 & 0xFF;
    
    // Advance PS segment
    rds_encoder.ps_segment = (rds_encoder.ps_segment + 1) % 4;
}

/**
 * Generate 57kHz RDS subcarrier modulated with data
 * This should be called from a timer interrupt at audio sample rate
 */
float RDS_GenerateSample(float sample_rate, uint32_t *phase_acc) {
    static uint8_t rds_group[13];
    static uint16_t bit_counter = 0;
    static uint8_t current_bit = 0;
    
    // Generate new group if needed
    if (bit_counter == 0) {
        RDS_GenerateGroup0A(rds_group);
    }
    
    // Get current bit
    uint8_t byte_index = bit_counter / 8;
    uint8_t bit_index = 7 - (bit_counter % 8);
    current_bit = (rds_group[byte_index] >> bit_index) & 0x01;
    
    // Advance bit counter at RDS bit rate
    static float bit_phase = 0;
    bit_phase += RDS_BITRATE / sample_rate;
    if (bit_phase >= 1.0f) {
        bit_phase -= 1.0f;
        bit_counter = (bit_counter + 1) % RDS_GROUP_LENGTH;
    }
    
    // Generate 57kHz carrier with BPSK modulation
    float phase_increment = (2.0f * PI * RDS_CARRIER_FREQ) / sample_rate;
    *phase_acc += (uint32_t)(phase_increment * 4294967296.0f);
    
    // BPSK: phase shift of 180° for bit value
    float carrier_phase = (*phase_acc / 4294967296.0f) * 2.0f * PI;
    if (current_bit) {
        carrier_phase += PI;  // 180° phase shift for '1'
    }
    
    return arm_sin_f32(carrier_phase) * 0.1f;  // 10% injection level
}

// ====================
// STEREO MPX GENERATOR
// ====================

#define PILOT_FREQ      19000.0f    // 19kHz pilot tone
#define SUBCARRIER_FREQ 38000.0f    // 38kHz stereo subcarrier

typedef struct {
    uint32_t pilot_phase;
    uint32_t subcarrier_phase;
    float audio_left;
    float audio_right;
} MPX_Generator;

static MPX_Generator mpx_gen = {0};

/**
 * Generate stereo MPX composite signal
 * Output = (L+R) + 0.1*19kHz_pilot + (L-R)*cos(38kHz)
 */
float MPX_GenerateSample(float left, float right, float sample_rate) {
    float composite = 0;
    
    // Main channel (L+R)
    float main_channel = (left + right) * 0.45f;  // 45% modulation each
    composite += main_channel;
    
    // 19kHz pilot tone (10% modulation)
    float pilot_increment = (2.0f * PI * PILOT_FREQ) / sample_rate;
    mpx_gen.pilot_phase += (uint32_t)(pilot_increment * 4294967296.0f);
    float pilot = arm_sin_f32((mpx_gen.pilot_phase / 4294967296.0f) * 2.0f * PI);
    composite += pilot * 0.1f;
    
    // 38kHz subcarrier with (L-R) DSB-SC modulation
    float subchannel = (left - right) * 0.45f;
    float sub_increment = (2.0f * PI * SUBCARRIER_FREQ) / sample_rate;
    mpx_gen.subcarrier_phase += (uint32_t)(sub_increment * 4294967296.0f);
    float subcarrier = arm_cos_f32((mpx_gen.subcarrier_phase / 4294967296.0f) * 2.0f * PI);
    composite += subchannel * subcarrier;
    
    return composite;
}

// ================
// AUDIO PROCESSING
// ================

#define PREEMPHASIS_TAU     75e-6f  // 75μs time constant (US standard)
#define SAMPLE_RATE         48000.0f

typedef struct {
    float last_input;
    float last_output;
    float alpha;  // Filter coefficient
} PreEmphasis_Filter;

static PreEmphasis_Filter preemph_left = {0};
static PreEmphasis_Filter preemph_right = {0};

/**
 * Initialize pre-emphasis filter (75μs)
 */
void Audio_InitPreEmphasis(PreEmphasis_Filter *filter, float sample_rate) {
    float fc = 1.0f / (2.0f * PI * PREEMPHASIS_TAU);  // Corner frequency ≈ 2.1kHz
    filter->alpha = 1.0f / (1.0f + sample_rate / (2.0f * PI * fc));
    filter->last_input = 0;
    filter->last_output = 0;
}

/**
 * Apply pre-emphasis filter
 */
float Audio_PreEmphasis(PreEmphasis_Filter *filter, float input) {
    // High-pass filter: y[n] = α*(y[n-1] + x[n] - x[n-1])
    float output = filter->alpha * (filter->last_output + input - filter->last_input);
    filter->last_input = input;
    filter->last_output = output;
    return output;
}

/**
 * Soft clipper/limiter to prevent overmodulation
 */
float Audio_SoftClip(float input, float threshold) {
    if (input > threshold) {
        return threshold + (input - threshold) / (1.0f + ((input - threshold) / 0.1f));
    } else if (input < -threshold) {
        return -threshold + (input + threshold) / (1.0f - ((input + threshold) / 0.1f));
    }
    return input;
}

/**
 * AGC (Automatic Gain Control)
 */
typedef struct {
    float gain;
    float target_level;
    float attack_coeff;
    float release_coeff;
} AGC_State;

static AGC_State agc = {
    .gain = 1.0f,
    .target_level = 0.7f,
    .attack_coeff = 0.01f,
    .release_coeff = 0.001f
};

float Audio_AGC(float input) {
    float output = input * agc.gain;
    float level = fabsf(output);
    
    // Adjust gain based on level
    if (level > agc.target_level) {
        // Attack: reduce gain quickly
        agc.gain -= (level - agc.target_level) * agc.attack_coeff;
    } else {
        // Release: increase gain slowly
        agc.gain += (agc.target_level - level) * agc.release_coeff;
    }
    
    // Limit gain range
    if (agc.gain < 0.1f) agc.gain = 0.1f;
    if (agc.gain > 2.0f) agc.gain = 2.0f;
    
    return output;
}

// ========================
// MAIN PROCESSING FUNCTION
// ========================

/**
 * Process complete audio chain: AGC → Pre-emphasis → MPX → RDS
 * Call this from audio sample rate interrupt (e.g., 48kHz)
 */
float FM_ProcessAudio(float left_in, float right_in) {
    // Step 1: AGC
    left_in = Audio_AGC(left_in);
    right_in = Audio_AGC(right_in);
    
    // Step 2: Pre-emphasis (75μs)
    float left_preemph = Audio_PreEmphasis(&preemph_left, left_in);
    float right_preemph = Audio_PreEmphasis(&preemph_right, right_in);
    
    // Step 3: Soft clipping to prevent overmodulation
    left_preemph = Audio_SoftClip(left_preemph, 0.9f);
    right_preemph = Audio_SoftClip(right_preemph, 0.9f);
    
    // Step 4: Generate stereo MPX composite
    float mpx_output = MPX_GenerateSample(left_preemph, right_preemph, SAMPLE_RATE);
    
    // Step 5: Add RDS subcarrier
    static uint32_t rds_phase = 0;
    float rds_signal = RDS_GenerateSample(SAMPLE_RATE, &rds_phase);
    mpx_output += rds_signal;
    
    // Final limiting to ±75kHz deviation
    mpx_output = Audio_SoftClip(mpx_output, 1.0f);
    
    return mpx_output;
}

// ===================
// MAIN INITIALIZATION
// ===================

/**
 * Initialize complete FM transmitter system
 */
void FM_Transmitter_Init(void) {
    // Initialize ADF4351 PLL at 88.5 MHz
    ADF4351_SPI_Init();
    ADF4351_Init(88500000);  // 88.5 MHz
    
    // Initialize audio processing
    Audio_InitPreEmphasis(&preemph_left, SAMPLE_RATE);
    Audio_InitPreEmphasis(&preemph_right, SAMPLE_RATE);
    
    // Initialize RDS
    RDS_Init("MYCALL  ", "This is a test of the RDS system - STM32F4 power!", 0x1234);
    
    // TODO: Initialize I2S/DAC for audio input/output
    // TODO: Initialize timer interrupt at 48kHz for audio processing
}

/**
 * Change transmit frequency
 */
void FM_SetFrequency(float freq_mhz) {
    uint32_t freq_hz = (uint32_t)(freq_mhz * 1000000.0f);
    ADF4351_SetFrequency(freq_hz);
}

/**
 * Update RDS text
 */
void FM_UpdateRDS(const char *ps_name, const char *radio_text) {
    strncpy(rds_encoder.data.ps_name, ps_name, 8);
    strncpy(rds_encoder.data.radio_text, radio_text, 64);
}

// ======
//  MAIN
// ======

int main(void) {
    // System initialization
    SystemInit();
    
    // Initialize FM transmitter
    FM_Transmitter_Init();
    
    // Set frequency to 88.5 MHz
    FM_SetFrequency(88.5f);

[King Croccy]

I think you have your parts mixed up. The BLF278 is a 300W high power mosfet, you would never use it for an exciters 1w output lol

What part do you mean?

Looks like a nice design though

[Up_North_Radio]

I think you have your parts mixed up. The BLF278 is a 300W high power mosfet, you would never use it for an exciters 1w output lol

What part do you mean?

Looks like a nice design though

Yes sorry, was looking at the wrong datasheet while typing was looking at the amp stage.

Lot more to work to be done but fell it might be worth a build.

[Albert H]

Since the ADF4351's integrated VCO already uses varactor tuning internally, we're essentially adding a second varactor in series that handles the audio modulation.

The key is in the loop filter design. By setting the PLL bandwidth to around 10kHz, we create a situation where the audio frequencies (50Hz-15kHz) sit above the loop bandwidth. This means the PLL doesn't try to correct the frequency variations we're deliberately introducing it only sees them as high-frequency noise and ignores them. The result should be clean FM modulation while maintaining the PLL's frequency lock on the carrier.

I'm well aware of the principles of FM generation and loop filter design in PLL synthesisers - I designed my first ones almost 50 years ago, so should have a handle on how they work by now!

Sadly, just slapping an additional varicap diode onto the tune pin isn't going to work. The internal structure of the IC includes a simple DC buffer amplifier between the external pin and the actual internal tuned circuit. Also, inside the IC, it's not really a tuned circuit (with inductance and capacitance) as you'd know it - it's a semiconductor-based analogue of the "real thing". You might get some result with introducing your modulating signal between the external loop filter and the tune pin of the IC, but you're unlikely to get much deviation - the circuit is designed to eliminate both slow and more rapid frequency changes, in an effort to ensure the best frequency stability. Sadly, you're barking up the wrong tree.

You could generate your carrier at some fraction of the output frequency, and multiply the resultant carrier up to the output frequency in an effort to achieve the required deviation, but each multiplication stage will introduce noise and spurs of its own, so the advantage of your ultra-clean signal generation is lost. Also, you can be sure that the PLL will "fight" against the modulation, so deviation linearity is sure to be abysmal.

There are other IC-based solutions used in some modern commercial equipment (the models you cite are just a small sub-set of this growing trend in transmitter design), but the vast majority of transmitter manufacturers are viewing a diminishing world-wide market, as "broadcasting" migrates on-line. There's little effort going into research and development of new technologies for this type of product that's going to be entirely obsolete in the forseeable future.

The manufacturers we deal with still use quite conventional designs, though one manufacturer has taken the NRG Kallitron twin oscillator and used it as a self-doubling exciter oscillator (as in the old NRG designs), but at higher power - their oscillator develops around 6 Watts at Band II after their fundamental rejection filter, and the thing is constructed directly on to a fairly substantial heatsink! They've used wide-swing varicaps with around 40V tuning voltage range, to be able to tune the whole band without adjustment. Their subsequent stages are all balanced amplifiers, based on pairs of FETs, and their "exciter" delivers a spectacularly clean 120 Watts anywhere in Band II to better than 40Hz accuracy, with no temperature or other drift that I could discover. The whole thing, includng a traditional linear power supply, fits into a 2U 19" case, and it's spectral purity is close to the best I've seen. Best of all, it requires no real calibration or maintenance - just set the frequency and the deviation sensitivity, and off it goes..... All the components used are through-hole, and the PLL is based on a Philips prescaler and a small boxful of CMOS logic. The frequency reference is one of those commercial oscillator blocks (that are remarkably cheap and highly stable), or there's facility for GPS frequency moderation if required.

There's little point in improving the wheel - it's been around for a long time, and it works well. Similarly, the "traditional" methods of transmitter design and construction really are the way to go for a dying market....

Generating stereo and RDS can be done in a single microprocessor - PCS have had a product like that for some time - but again, it's really not worth the effort. PICs are great for RDS, and I'd defy anyone to better my stereo coder design!

[EFR]

Btw, why first message has much of AI feeling on it?

[EFR]

ADF4351 has internal VCO running between 2000 - 4400Mhz, so it is more protected against powersupply noise.

Does BFP420 turn to an Ghz range oscillator? Ft of 45Ghz might make it possible?

[Albert H]

Most of these signal generator ICs seem to use GHz-range VCOs (try varying the bias voltage to the bases in a standard audio range multivibrator to vary the frequency, and you'll see the technique). The VCO then drives dividers and Fourier synthesis networks to generate pseudo sine outputs. Unfortunately, the original poster doesn't appreciate the internal structure of the IC he's trying to use, so his attempts at FM generation with the IC he proposed is doomed to failure.

Modern commercial transmitter designs mostly use FET Colpitts or Hartley oscillators, frequency mulipliers and one of the LMX-series PLLs. Some have moved to the Arduino or similar SBC to load the data into the PLL IC, and to provide various pieces of status monitoring, including heatsink temperatures, VSWR of the load, and even silence detection and alarms. All manufacturers compete to provide the minimum number of adjustment points to simplify calibration and maintenance of their unit. They also design for reliability, often quoting massive "up-time" percentages, and emphasising their ease of maintenance.

Most designs follow a similar topology, and the only real variations are use of linear or switched-mode supplies, power output, physical size, and price! Almost all are designed for 19" rack mounting, and most have status indication on an LCD display. Most offer remote control and comprehensive telemetry.

The build quality of most commercial transmitters is usually exemplary, and all are designed to conform to the most stringent performance parameters, so that they can conform to broadcast regulations in any part of the world. The most stringent are (probably) the German and the Japanese specifications, though most countries have brought their specifications pretty much into line with these.

Incidentally, EFR, I see what you mean about the possibility of AI generated content.....

[EFR]

As an idea/project, it is interesting way to think around the box.

I hope we see first prototype soon?

[Up_North_Radio]

Yes I fed the paper and the HTML I created into the AI Claude to see if it would format it for the forum did make it sound a little robotic took out a lot of what I wrote and replaced it.

Won't lie if I had not would of been full with errors.

Still I do feel it would be worth looking into maybe people might see the value in the extra goodies that can come with such a design such as the RDS and others.

Not only that from a builder perspective gives a lot more options.

Spent a fair amount of time looking over this idea looking at the schematics and coming up with a plan of attack.

While the original is a great design out the box I think with some extra tweeks could really have a one stop shop driver which if you think about the long run might actual be better value and also a extra cost option that I think if was available people would pick.

Anyway got some attention on the idea now just a case of see if anyone wants to partner up and work on this or maybe we could build some test boards and post the results.

Thinking caps on!

PS I may use AI at times to format things not being in the best of health atm.

[Up_North_Radio]

ADF4351 has internal VCO running between 2000 - 4400Mhz, so it is more protected against powersupply noise.

Does BFP420 turn to an Ghz range oscillator? Ft of 45Ghz might make it possible?

25 GHz fT and 1.1 dB noise for the BFP420 and says up to 10ghz. So maybe not.

Couople evenings with Lcsc and JLC pcb catalogs and we have ready made files to order fully build units from JLC pcb?

This is kind of what I was looking for maybe some help to design the new board and get some test ones from JL ordered up.

[jvok]

There are a few synthesiser ICs from TI and AD that can be used with an external VCO, so you could have a traditional VCO/PLL design but with ICs you can actually still buy from mainstream distributors. Most of them cost more than an old-stock TSA5511 or SAA1057 though.

Tbh I think the old school 7400 based PLL is still the best way to go. The ICs are dirt cheap, available anywhere and aren't likely to go obsolete overnight like specialist PLL chips. Even if the western manufacturers pack it in theres a half dozen Chinese brands that make clones, and because the ICs are so simple I'd be much happier trusting them than most other cloned parts. Only downside is higher parts count but if you made it SMT it would still be pretty tiny, and you could have them churned out by JLC etc for pennies each.

I also have an idea I've been meaning to try out some time to use the timer peripheral of an MCU in place of the divide-by-N IC, then you could have MCU control (LCDs, anti-theft, whatever) but still with a CMOS PLL. Could probably use one of the other timers for the reference too, so you'd just have the MCU, couple of D-types for prescaler and an XOR for phase detector.

[EFR]

RP2040 can count well up to 150Mhz and over, some hams are done PLL stuff with it.

They have used PWM output to drive an fet, to get more than 5V to the VCO tuning. Tuning voltage filters are quite needed to keep it clean.

[Albert H]

Jvok: I tried using the timers in a couple of MCUs, but they're not really precise (and affected by other stuff going on in the processor) and their outputs are frequently seen to "jitter". The simplest anti-theft measures are usually the best, and using diode-programmed counter ICs buried in epoxy is difficult for the rig thieves and their "engineers". Also a dose of Shigella gives long-lasting protection, because the victims really won't want to steal any more rigs after they've been infected. Incidentally, rubber gloves and other basic protections seldom work with Shigella, which is why it's used to train lab-techs and Doctors in handling contagions!

I'll happily provide the circuits I commonly use for my VCOs and PLLs. You're right about smd versions - the whole PLL and VCO can be built on to a very small board. I designed our most recent version to fit neatly inside a small tinplate box, and when it's programmed (by cutting tracks), tested, and the supply, modulation and output leads are connected, the tinplate box can be filled with epoxy resin. We've found that potting them - including the reference crystal - makes for great long-term stability, and the whole thing costs just a few Euros a time!

My latest VCO uses a hybrid design, mixing FETs (for their high input impedance to maximise oscillator coil "Q") and small RF bipolar transistors (for their current handling and low noise). The carrier noise and adjacent purity is exemplary. Generation remains at half the output frequency, to eliminate the RF feedback problems of at-frequency designs. The output is settable between 80 MHz and 110 MHz without any adjustment. Modulation linearity is excellent (leading to very low modulation distortion), and the loop filter allows audio down to around 21Hz. It's not the perfect solution, but it's cheap and effective!